A common requirement of current integrated circuit manufacturing and packaging is the use of interposers to receive multiple integrated circuit dies. The use of through vias or through silicon vias (“TSVs”) is increasing. These through vias allow electrical coupling between integrated circuit dies and components mounted on one side of an interposer, and terminals such as solder balls mounted on the opposite side of the interposer. Further, the use of TSV technologies with silicon interposer substrates enable wafer level processing (“WLP”) of the interposer assemblies. A form factor useful for mounting multiple integrated circuit dies (ICs) is to use a wafer substrate such as a semiconductor wafer with TSVs to make through wafer connections. The ICs may be mounted on one side of the silicon wafer, and at least some terminals of the ICs may be coupled to the TSVs in the interposer. Board level connections such as solder balls, bumps, or columns may be formed on the opposite side of the interposer and coupled to the ICs using the TSVs. The assembly may now be mounted to a circuit board using solder reflow techniques and the solder bumps or balls. The use of TSV through wafer connections also allows for the capability of vertical stacking of the assemblies, enabling manufacturers to increase integrated circuit component density and system performance without increasing circuit board area. This technique is increasingly applicable to increasing memory or storage device density, for example, without added circuit board area. As demand for hand held and portable devices such as smart phones and tablet computers increases, board area and board size restrictions also increases, and the use of the interposer assemblies and TSVs can meet these requirements. These techniques apply to semiconductor wafers such as silicon wafers, but may also apply to other interposer materials, for example BT resin and other interposer materials, where through via connections, conductive patterning for connecting components, and component mounting may be performed.
During processing of the dies mounted on the wafer interposer, which may be referred to as a “die on wafer” (“DOW”) assembly, a wafer dicing step is performed to separate the individual integrated circuit die components, each of which may include several ICs mounted on one side of the interposer, and a group of circuit board connections such as the solder columns, solder bumps or solder balls mounted on the opposite side, into separate assembly units. This process may be referred to as “singulation”. During wafer sawing, a wet blade is used to saw through the wafer in scribe areas in gaps (“scribe lines”) between the ICs. Conventional sawing or “dicing” techniques are available for semiconductor wafers. An adhesive tape known as dicing tape is typically used to secure the wafer and keep it stationary during dicing. During dicing, a wet sawing operation cuts the wafer along the scribe lines. However a DOW wafer assembly has integrated circuit dies mounted on one side and the solder balls or solder bumps on the other side. Neither side of the DOW assembly is free from mounted objects. Neither side of the DOW assembly provides a simple planar surface for mounting to a conventional dicing tape. Because the sawing operation in the dicing process is a mechanical operation using a high speed rotating blade and jetting water, vibration occurs. In attempts to dice the assemblies using conventional approaches, damage to the interposer in the form of wafer chipping, damage to the ICs, including demounting of the ICs, and damage to the solder balls has been observed. Water penetration inducing die fly or die tilt has been observed when dicing. Tape peel-off in between the tape adhesive and silicon interposer induced by a non-planar surface on either side of interposer during the dicing operation has been observed. Any of these problems lead to failures which can cause large loss of known good dies (“KGDs”) at the dicing stage, which greatly increases the cost and lowers yield of the circuit assemblies.
A continuing need thus exists for methods and systems to efficiently perform dicing for interposer assemblies without damage to the interposer, to the mounted ICs or to the connection terminals. Improvements are needed to increase manufacturing yields, and to reduce damage to finished devices currently experienced when using the known methods.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.